Invention Grant
- Patent Title: Semiconductor switching devices and fabrication methods
- Patent Title (中): 半导体开关器件及其制造方法
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Application No.: US12207110Application Date: 2008-09-09
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Publication No.: US07709314B2Publication Date: 2010-05-04
- Inventor: Raminda Udaya Madurawe
- Applicant: Raminda Udaya Madurawe
- Applicant Address: US CA Santa Clara
- Assignee: Tier Logic, Inc.
- Current Assignee: Tier Logic, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Tran & Associates
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
Methods of fabricating low temperature semiconductor thin film switching devices are described. A method includes: forming one or more metal lines on a substrate; forming a conductive contact to a said metal line thru an insulator layer above the metal lines; forming a thin film N-type and P-type conducting transistor pair having: a contiguous amorphous silicon first geometry above the insulator layer, said first geometry including an N-type transistor region, a P-type transistor region, and a common region between the transistor regions fully covering the contact; and a gate dielectric layer above the first geometry; and a contiguous amorphous silicon second geometry above the gate dielectric layer including transistor regions that cross over the first geometry transistor regions; forming a silicide of first and second amorphous silicon geometry surfaces with a deposited metallic material, the silicided surfaces including: said second geometry surface; and said first geometry surface not covered by the second geometry, which includes the surface of the region covering the contact; depositing an insulating material; and forming conductive contacts and top metal interconnects.
Public/Granted literature
- US20090004791A1 SEMICONDUCTOR SWITCHING DEVICES AND FABRICATION METHODS Public/Granted day:2009-01-01
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