Invention Grant
- Patent Title: Methods of fabricating transistors including dielectrically-supported gate electrodes
- Patent Title (中): 制造包括介电支撑栅电极的晶体管的方法
-
Application No.: US11493069Application Date: 2006-07-26
-
Publication No.: US07709269B2Publication Date: 2010-05-04
- Inventor: Richard Peter Smith , Scott T. Sheppard
- Applicant: Richard Peter Smith , Scott T. Sheppard
- Applicant Address: US NC Durham
- Assignee: Cree, Inc.
- Current Assignee: Cree, Inc.
- Current Assignee Address: US NC Durham
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Main IPC: H01L21/338
- IPC: H01L21/338

Abstract:
Transistors are fabricated by forming a protective layer having a first opening extending therethrough on a substrate, forming a dielectric layer on the protective layer having a second opening extending therethrough that is wider than the first opening, and forming a gate electrode in the first and second openings. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the first opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion on portions of the dielectric layer outside the second opening. Related devices and fabrication methods are also discussed.
Public/Granted literature
Information query
IPC分类: