Invention Grant
US07707707B2 Method for providing a temporary deep shunt on wafer structures for electrostatic discharge protection during processing
失效
在晶片结构上提供临时深度分流的方法,用于处理期间的静电放电保护
- Patent Title: Method for providing a temporary deep shunt on wafer structures for electrostatic discharge protection during processing
- Patent Title (中): 在晶片结构上提供临时深度分流的方法,用于处理期间的静电放电保护
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Application No.: US11612539Application Date: 2006-12-19
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Publication No.: US07707707B2Publication Date: 2010-05-04
- Inventor: David John Seagle
- Applicant: David John Seagle
- Applicant Address: NL Amsterdam
- Assignee: Hitachi Global Storage Technologies Netherlands B.V.
- Current Assignee: Hitachi Global Storage Technologies Netherlands B.V.
- Current Assignee Address: NL Amsterdam
- Main IPC: G11B5/23
- IPC: G11B5/23

Abstract:
A method of temporarily protecting an electrically sensitive component from damage due to electrostatic discharge includes defining a shunt having first and second leads electrically connected in parallel with the component and separated by a gap. A portion of a shield layer is deposited to form the shunt between the first and second leads to span the gap therebetween and form a shunted assembly. The shunted assembly and component are lapped to form the ABS at the location of the component, a sacrificial carbon overcoat is deposited on the ABS, and additional processing is performed on the shunted assembly. A portion of the shunted assembly, the shunt, and portions of the sacrificial carbon overcoat are then removed to form an electrical open for an unshunted assembly having ABS features comprising an air bearing cavity/deep gap at a former location of the shunted assembly.
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