A semiconductor memory device includes: a memory cell array including a plurality of memory cells arranged in rows and columns for holding information, each of the memory cells having a control gate; a plurality of word lines extending in a row direction, each of the word lines being connected to the control gates of the memory cells of a corresponding row of the memory cell array; a plurality of bit lines extending in a column direction and connected to sources or drains of the memory cells; a row decoder for selecting any of the plurality of word lines; a column decoder for selecting any of the plurality of bit lines; a charge pump circuit for generating a voltage higher than a supply voltage; and a first switch located in a connection path between the row decoder and the charge pump circuit.