Invention Grant
- Patent Title: Structure design for minimizing on-chip interconnect inductance
- Patent Title (中): 用于最小化片上互连电感的结构设计
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Application No.: US11688903Application Date: 2007-03-21
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Publication No.: US07705696B2Publication Date: 2010-04-27
- Inventor: Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
- Applicant: Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Thomas, Kayden, Horstemeyer & Risley
- Main IPC: H01P3/08
- IPC: H01P3/08
Abstract:
A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line.
Public/Granted literature
- US20080231393A1 STRUCTURE DESIGN FOR MINIMIZING ON-CHIP INTERCONNECT INDUCTANCE Public/Granted day:2008-09-25
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