Invention Grant
US07705642B2 Simplified bias circuitry for differential buffer stage with symmetric loads
有权
具有对称负载的差分缓冲级的简化偏置电路
- Patent Title: Simplified bias circuitry for differential buffer stage with symmetric loads
- Patent Title (中): 具有对称负载的差分缓冲级的简化偏置电路
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Application No.: US11703634Application Date: 2007-02-08
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Publication No.: US07705642B2Publication Date: 2010-04-27
- Inventor: Tony Mai
- Applicant: Tony Mai
- Applicant Address: CA Kanata, Ontario
- Assignee: Mosaid Technologies Incorporated
- Current Assignee: Mosaid Technologies Incorporated
- Current Assignee Address: CA Kanata, Ontario
- Main IPC: H03L7/06
- IPC: H03L7/06
Abstract:
A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the Vnbias between the P-type transistor and the diode connected transistor. The circuit is simpler than conventional biasing circuits that employ feedback and operational amplifiers.
Public/Granted literature
- US20080191782A1 Simplified bias circuitry for differential buffer stage with symmetric loads Public/Granted day:2008-08-14
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