Invention Grant
- Patent Title: Stacked semiconductor package that prevents damage to semiconductor chip when wire-bonding and method for manufacturing the same
- Patent Title (中): 堆焊半导体封装,防止导线接合时对半导体芯片的损坏及其制造方法
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Application No.: US11940522Application Date: 2007-11-15
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Publication No.: US07705468B2Publication Date: 2010-04-27
- Inventor: Cheol Ho Joh
- Applicant: Cheol Ho Joh
- Applicant Address: KR Kyoungki-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Kyoungki-do
- Agency: Ladas & Parry LLP
- Priority: KR10-2007-0103880 20071016
- Main IPC: H01L23/52
- IPC: H01L23/52

Abstract:
A stacked semiconductor package includes a substrate having first and second contact pads. A first stacked package group is disposed on the substrate, and the first stacked package group includes first semiconductor chips stacked in a stair form to expose first edge bonding pads. First conductive wires are used to electrically couple the first edge bonding pads and the first contact pads. An adhesive member is disposed on the uppermost first semiconductor chip, and a second stacked package group is disposed on the adhesive member. The second stacked package group includes second semiconductor chips that are stacked in a stair form to expose second edge bonding pads. When the second stacked package group is disposed on the adhesive member, the bottommost second semiconductor chips is aligned with the uppermost first semiconductor chip. Second conductive wires are used to electrically couple the second edge bonding pads and the second contact pads.
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