Invention Grant
US07705406B2 Transistor array with selected subset having suppressed layout sensitivity of threshold voltage
有权
具有选定子集的晶体管阵列具有抑制阈值电压的布局灵敏度
- Patent Title: Transistor array with selected subset having suppressed layout sensitivity of threshold voltage
- Patent Title (中): 具有选定子集的晶体管阵列具有抑制阈值电压的布局灵敏度
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Application No.: US12464211Application Date: 2009-05-12
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Publication No.: US07705406B2Publication Date: 2010-04-27
- Inventor: Victor Moroz , Dipankar Pramanik
- Applicant: Victor Moroz , Dipankar Pramanik
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Warren Wolfeld Haynes Beffel & Wolfeld LLP
- Main IPC: H01L29/76
- IPC: H01L29/76
Abstract:
A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout.
Public/Granted literature
- US20090236673A1 METHOD FOR SUPPRESSING LAYOUT SENSITIVITY OF THRESHOLD VOLTAGE IN A TRANSISTOR ARRAY Public/Granted day:2009-09-24
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