Invention Grant
- Patent Title: Test inserts and interconnects with electrostatic discharge structures
- Patent Title (中): 测试插件和具有静电放电结构的互连
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Application No.: US10230836Application Date: 2002-08-29
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Publication No.: US07705349B2Publication Date: 2010-04-27
- Inventor: David R. Hembree , Salman Akram
- Applicant: David R. Hembree , Salman Akram
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L23/58
- IPC: H01L23/58

Abstract:
An apparatus and method for providing external electrostatic discharge (ESD) protection to a semiconductor device, which may or may not include its own ESD protection, are provided. An ESD structure may be associated with each interconnect, either individually or shared between two or more interconnects. Each interconnect includes a contact tip for establishing a temporary electrical connection with a bond pad of the semiconductor device and a contact pad for electrically interfacing the bond pad with external burn-in and/or test equipment. The ESD structure may be implemented, for example, as a fusible element or a shunting element, such as a pair of diodes, a diode-resistor network, or a pair of transistors. The interconnect may be employed as part of an insert including a plurality of interconnects that provides ESD protection to a plurality of integrated circuits of at least one semiconductor device.
Public/Granted literature
- US20040041168A1 Test insert with electrostatic discharge structures and associated methods Public/Granted day:2004-03-04
Information query
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