Invention Grant
US07702944B2 Dynamic frequency scaling sequence for multi-gigahertz microprocessors 失效
用于多千兆赫微处理器的动态频率缩放序列

Dynamic frequency scaling sequence for multi-gigahertz microprocessors
Abstract:
The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.
Information query
Patent Agency Ranking
0/0