Invention Grant
US07702061B2 High speed hybrid structure counter having synchronous timing and asynchronous counter cells
失效
具有同步定时和异步计数器单元的高速混合结构计数器
- Patent Title: High speed hybrid structure counter having synchronous timing and asynchronous counter cells
- Patent Title (中): 具有同步定时和异步计数器单元的高速混合结构计数器
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Application No.: US12002614Application Date: 2007-12-17
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Publication No.: US07702061B2Publication Date: 2010-04-20
- Inventor: Zhuyan Shao , Juan Qiao
- Applicant: Zhuyan Shao , Juan Qiao
- Applicant Address: US CA San Jose
- Assignee: Integrated Device Technology, Inc.
- Current Assignee: Integrated Device Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Finnegan, et al.
- Main IPC: H03K21/00
- IPC: H03K21/00 ; H03K23/00
Abstract:
A multi-bit counter is provided. The multi-bit counter includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals. The multi-bit counter also includes at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal.
Public/Granted literature
- US20090154637A1 High speed hybrid structure counter having synchronous timing and asynchronous counter cells Public/Granted day:2009-06-18
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