Invention Grant
- Patent Title: Integrated circuit package system for chip on lead
- Patent Title (中): 集成电路封装系统，用于芯片上的引线
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Application No.: US11856879Application Date: 2007-09-18
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Publication No.: US07701042B2Publication Date: 2010-04-20
- Inventor: Shao Jian Chen , Wei Qiang Jin , Bhoy Ching , Taw Ming Lau
- Applicant: Shao Jian Chen , Wei Qiang Jin , Bhoy Ching , Taw Ming Lau
- Applicant Address: SG Singapore
- Assignee: Stats Chippac Ltd.
- Current Assignee: Stats Chippac Ltd.
- Current Assignee Address: SG Singapore
- Agent Mikio Ishimaru
- Main IPC: H01L23/495
- IPC: H01L23/495
Abstract:
An integrated circuit package system includes providing an integrated circuit die having planar dimensions; forming a lead extended across one of the planar dimensions of the integrated circuit die; and applying an adhesive layer over the lead of a side opposite the integrated circuit die.
Public/Granted literature
- US20080073781A1 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR CHIP ON LEAD Public/Granted day:2008-03-27
Information query
IPC分类:
