A semiconductor memory device having a memory cell array with sub-memory cell arrays arranged in a bit line direction and a word line direction which is perpendicular to the bit line direction. The memory cell arrays including a plurality of memory cells. The memory device further including sense amplifying portions arranged between the sub-memory cell arrays in the bit line direction, contact and conjunction portions arranged between the sub-memory cell arrays in the word line direction and conjunction portions arranged between the sense amplifiers in the word line direction. A main word line overlaps a word line between the sub-memory cell arrays arranged in the word line direction.