Invention Grant
- Patent Title: Two-bits per cell not-and-gate (NAND) nitride trap memory
- Patent Title (中): 每个单元非栅极(NAND)氮化物陷阱存储器的两位
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Application No.: US12123302Application Date: 2008-05-19
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Publication No.: US07675787B2Publication Date: 2010-03-09
- Inventor: Hsiang-Lan Lung
- Applicant: Hsiang-Lan Lung
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX International Co., Ltd.
- Current Assignee: MACRONIX International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate between the first source/drain region and the second source/drain region. A plurality of memory cells are disposed on the main surface above the well region. Each memory cell includes a first oxide layer formed on the main surface of the substrate, a charge storage layer disposed above the first oxide layer relative to the main surface of the semiconductor substrate and a second oxide layer disposed above the charge storage layer relative to the main surface of the semiconductor substrate. A plurality of wordlines are disposed above the second oxide layer relative to the main surface of the semiconductor substrate.
Public/Granted literature
- US20080259691A1 Two-Bits Per Cell Not-AND-Gate (NAND) Nitride Trap Memory Public/Granted day:2008-10-23
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