Invention Grant
- Patent Title: Combined volatile nonvolatile array
- Patent Title (中): 组合易失性非易失性阵列
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Application No.: US11999684Application Date: 2007-12-05
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Publication No.: US07675775B2Publication Date: 2010-03-09
- Inventor: Andreas Scade , Stefan Guenther
- Applicant: Andreas Scade , Stefan Guenther
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G11C14/00
- IPC: G11C14/00
Abstract:
A memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines.
Public/Granted literature
- US20090147578A1 Combined volatile nonvolatile array Public/Granted day:2009-06-11
Information query
