Invention Grant
US07675334B2 Delay locked loop circuit and semiconductor integrated circuit device
有权
延迟锁定环电路和半导体集成电路器件
- Patent Title: Delay locked loop circuit and semiconductor integrated circuit device
- Patent Title (中): 延迟锁定环电路和半导体集成电路器件
-
Application No.: US12354391Application Date: 2009-01-15
-
Publication No.: US07675334B2Publication Date: 2010-03-09
- Inventor: Takashi Kawamoto
- Applicant: Takashi Kawamoto
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Miles & Stockbridge P.C.
- Priority: JP2006-067243 20060313
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.
Public/Granted literature
- US20090134924A1 DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2009-05-28
Information query