Invention Grant
US07675333B2 Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof 有权
在宽频率范围内具有等间隔相位的多相延迟锁相环及其方法

Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof
Abstract:
A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.
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