Invention Grant
US07675333B2 Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof
有权
在宽频率范围内具有等间隔相位的多相延迟锁相环及其方法
- Patent Title: Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof
- Patent Title (中): 在宽频率范围内具有等间隔相位的多相延迟锁相环及其方法
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Application No.: US11760782Application Date: 2007-06-10
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Publication No.: US07675333B2Publication Date: 2010-03-09
- Inventor: Prasenjit Bhowmik , Sundararajan Krishnan , Sriram Ganesan
- Applicant: Prasenjit Bhowmik , Sundararajan Krishnan , Sriram Ganesan
- Applicant Address: IN Bangalore
- Assignee: Cosmic Circuits Private Limited
- Current Assignee: Cosmic Circuits Private Limited
- Current Assignee Address: IN Bangalore
- Agency: Evergreen Valley Law Group, P.C.
- Agent Kanika Radhakrishnan
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.
Public/Granted literature
- US20070285138A1 MULTI-PHASE DELAY LOCKED LOOP WITH EQUALLY-SPACED PHASES OVER A WIDE FREQUENCY RANGE AND METHOD THEREOF Public/Granted day:2007-12-13
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