Invention Grant
- Patent Title: Raised vertical channel transistor device
- Patent Title (中): 升高的垂直沟道晶体管器件
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Application No.: US12265734Application Date: 2008-11-06
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Publication No.: US07675109B2Publication Date: 2010-03-09
- Inventor: Shian-Jyh Lin
- Applicant: Shian-Jyh Lin
- Applicant Address: TW Kueishan, Tao-Yuan Hsien
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
- Agent Winston Hsu
- Priority: TW95125767A 20060714
- Main IPC: H01L29/78
- IPC: H01L29/78
Abstract:
A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form drain, vertical channel and source in the opening. Subsequently, sidewall gate dielectric and sidewall gate electrode are formed on the vertical channel. The present invention is suited for dynamic random access memory (DRAM) devices, particularly suited for very high-density trench-capacitor DRAM devices.
Public/Granted literature
- US20090065857A1 RAISED VERTICAL CHANNEL TRANSISTOR DEVICE Public/Granted day:2009-03-12
Information query
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