Invention Grant
- Patent Title: Methods of forming an integrated circuit package
- Patent Title (中): 形成集成电路封装的方法
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Application No.: US11218998Application Date: 2005-09-01
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Publication No.: US07674652B2Publication Date: 2010-03-09
- Inventor: Warren M. Farnworth , Jerry M. Brooks
- Applicant: Warren M. Farnworth , Jerry M. Brooks
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder PC
- Main IPC: H01L21/50
- IPC: H01L21/50 ; H01L21/48 ; H01L21/44

Abstract:
A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.
Public/Granted literature
- US20060014317A1 Integrated circuit package having reduced interconnects Public/Granted day:2006-01-19
Information query
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