Invention Grant
- Patent Title: Mask pattern inspection method, exposure condition verification method, and manufacturing method of semiconductor device
- Patent Title (中): 掩模图案检查方法,曝光条件验证方法和半导体器件的制造方法
-
Application No.: US11480382Application Date: 2006-07-05
-
Publication No.: US07674570B2Publication Date: 2010-03-09
- Inventor: Ichirota Nagahama , Yuichiro Yamazaki , Atsushi Onishi
- Applicant: Ichirota Nagahama , Yuichiro Yamazaki , Atsushi Onishi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2005-197522 20050706
- Main IPC: G03F7/20
- IPC: G03F7/20

Abstract:
A mask pattern inspection method includes: transferring a mask pattern onto a conductor substrate or a semiconductor substrate; preparing a sample including a substrate surface pattern in an electrically conductive state to the substrate, the substrate surface pattern being constituted of a convex pattern or a concave pattern each having a shape in accordance with the transferred mask pattern, or a surface layer obtained by filling the concave pattern with a material; irradiating the sample with an electron beam to detect at least one of a secondary electron, a reflected electron and a backscattered electron generated from the surface of the sample, thereby acquiring an image of the sample surface; and inspecting the mask pattern on the basis of the image.
Public/Granted literature
Information query
IPC分类: