Invention Grant
US07672827B1 Method and system for simulation of analog/digital interfaces with analog tri-state ioputs
失效
用模拟三态ioput模拟/数字接口的方法和系统
- Patent Title: Method and system for simulation of analog/digital interfaces with analog tri-state ioputs
- Patent Title (中): 用模拟三态ioput模拟/数字接口的方法和系统
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Application No.: US09648540Application Date: 2000-08-28
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Publication No.: US07672827B1Publication Date: 2010-03-02
- Inventor: Alexander D. Schapira , Asha Chandra , Jonathan A. Eiseman
- Applicant: Alexander D. Schapira , Asha Chandra , Jonathan A. Eiseman
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system and method for simulating the electrical operation of a mixed analog/digital system includes the capability for analog circuit block inputs to respond to the condition in which digital gate outputs connected to the analog circuit block input are presented in high-impedance or floating signal states, thereby providing for simulation of a wide variety of mixed analog/digital designs in which this condition occurs. In a simulated design, an analog input of one or more analog circuit blocks is transformed into an analog tri-statable input-output referred to as an ioput. The ioput is capable of driving an analog signal when the digital gate outputs connected to the analog block input are presented in a high-impedance Z state; otherwise, the ioput acts as an analog input to the analog circuit block.
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