Invention Grant
- Patent Title: Low power chip architecture
- Patent Title (中): 低功耗芯片架构
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Application No.: US10879111Application Date: 2004-06-30
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Publication No.: US07672694B2Publication Date: 2010-03-02
- Inventor: Sridevan Parameswaran , Jorgen Peddersen , Ashley Partis
- Applicant: Sridevan Parameswaran , Jorgen Peddersen , Ashley Partis
- Applicant Address: JP Tokyo
- Assignee: Canon Kabushiki Kaisha
- Current Assignee: Canon Kabushiki Kaisha
- Current Assignee Address: JP Tokyo
- Agency: Fitzpatrick, Cella, Harper & Scinto
- Priority: AU2003903480 20030707
- Main IPC: H04M1/00
- IPC: H04M1/00 ; H04L12/28 ; H04J3/16 ; G06F3/00

Abstract:
An architecture for selectively powering a receive module (108) is disclosed. The architecture comprises the receive module (108) which is functionally adapted, while power is applied to the receive module (108) by a power module (601), and after a power-up time interval has elapsed, to process a traffic packet. The architecture further comprises the power module (601) that is adapted to apply power to the receive module 108 dependent upon arrival of a wake-up packet.
Public/Granted literature
- US20050007972A1 Low power chip architecture Public/Granted day:2005-01-13
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