Invention Grant
US07672181B2 Semiconductor memory, test method of semiconductor memory and system
失效
半导体存储器,半导体存储器和系统的测试方法
- Patent Title: Semiconductor memory, test method of semiconductor memory and system
- Patent Title (中): 半导体存储器,半导体存储器和系统的测试方法
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Application No.: US12130578Application Date: 2008-05-30
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Publication No.: US07672181B2Publication Date: 2010-03-02
- Inventor: Kaoru Mori , Kota Hara , Jun Ohno
- Applicant: Kaoru Mori , Kota Hara , Jun Ohno
- Applicant Address: JP Tokyo
- Assignee: Fujitsu Microelectronics Limited
- Current Assignee: Fujitsu Microelectronics Limited
- Current Assignee Address: JP Tokyo
- Agency: Arent Fox LLP
- Priority: JP2007-210091 20070810
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily.
Public/Granted literature
- US20090040851A1 SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM Public/Granted day:2009-02-12
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