Invention Grant
US07671652B2 Logic circuit for use in a latch circuit and a data reading circuit or the like which includes such a latch circuit
失效
用于锁存电路的逻辑电路和包括这种锁存电路的数据读取电路等
- Patent Title: Logic circuit for use in a latch circuit and a data reading circuit or the like which includes such a latch circuit
- Patent Title (中): 用于锁存电路的逻辑电路和包括这种锁存电路的数据读取电路等
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Application No.: US11576682Application Date: 2005-10-04
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Publication No.: US07671652B2Publication Date: 2010-03-02
- Inventor: Yasushi Amamiya
- Applicant: Yasushi Amamiya
- Applicant Address: JP Tokyo
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2004-292678 20041005
- International Application: PCT/JP2005/018342 WO 20051004
- International Announcement: WO2006/038612 WO 20060413
- Main IPC: H03K3/00
- IPC: H03K3/00
Abstract:
A logic circuit is provided with a first differential transistor pair (Q1, Q2) operable in response to a data signal input thereto; a current source for supplying a current to the first differential transistor pair (Q1, Q2); a first transistor (Q5) connected between a common emitter of the first differential transistor pair (Q1, Q2) and the current source, and operable in response to a clock signal input thereto; and a first potential stabilizing circuit (30a) connected to a first junction between the common emitter of the first differential transistor pair (Q1, Q2) and a collector of the first transistor (Q5), for stabilizing a potential at said first junction.
Public/Granted literature
- US20080030234A1 Logic Circuit Public/Granted day:2008-02-07
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