Invention Grant
US07671362B2 Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing
失效
用于确定双镶嵌加工的最佳种子和衬层层厚度的测试结构
- Patent Title: Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing
- Patent Title (中): 用于确定双镶嵌加工的最佳种子和衬层层厚度的测试结构
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Application No.: US11953568Application Date: 2007-12-10
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Publication No.: US07671362B2Publication Date: 2010-03-02
- Inventor: Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
- Applicant: Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
- Applicant Address: US NY Armonk US CA Sunnyvale
- Assignee: International Business Machines Corporation,Advanced Micro Devices, Inc. (AMD)
- Current Assignee: International Business Machines Corporation,Advanced Micro Devices, Inc. (AMD)
- Current Assignee Address: US NY Armonk US CA Sunnyvale
- Agency: Cantor Colburn LLP
- Agent Wenjie Li
- Main IPC: H01L23/58
- IPC: H01L23/58
Abstract:
A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.
Public/Granted literature
- US20090146143A1 TEST STRUCTURE FOR DETERMINING OPTIMAL SEED AND LINER LAYER THICKNESSES FOR DUAL DAMASCENE PROCESSING Public/Granted day:2009-06-11
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