Invention Grant
- Patent Title: Methods of forming semiconductor constructions
- Patent Title (中): 形成半导体结构的方法
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Application No.: US12111335Application Date: 2008-04-29
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Publication No.: US07670898B2Publication Date: 2010-03-02
- Inventor: Kunal R. Parekh
- Applicant: Kunal R. Parekh
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/8234
- IPC: H01L21/8234

Abstract:
The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at least two segments separated by a gap. Additional semiconductor material is then grown over the dielectric material and within the gap. Subsequently, a transistor is formed to comprise source/drain regions within the additional semiconductor material, and to comprise a channel between the source/drain regions. At least one of the source/drain regions is primarily directly over a segment of the dielectric material, and the channel is not primarily directly over any segment of the dielectric material. The invention also includes constructions comprising partial SOI corresponding to segments of dielectric material, and transistors having at least one source/drain region primarily directly over a segment of dielectric material, and a channel that is not primarily directly over any segment of the dielectric material.
Public/Granted literature
- US20080199990A1 Semiconductor Constructions, and Methods of Forming Semiconductor Constructions Public/Granted day:2008-08-21
Information query
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