Invention Grant
US07657853B2 Verification apparatus, design verification method, and computer aided design apparatus
失效
设计验证装置,设计验证方法和计算机辅助设计装置
- Patent Title: Verification apparatus, design verification method, and computer aided design apparatus
- Patent Title (中): 设计验证装置,设计验证方法和计算机辅助设计装置
-
Application No.: US11589170Application Date: 2006-10-30
-
Publication No.: US07657853B2Publication Date: 2010-02-02
- Inventor: Mitsuru Sato , Takehiro Yamazaki
- Applicant: Mitsuru Sato , Takehiro Yamazaki
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Priority: JP2006-177437 20060628
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
According to the present invention, in a CAD apparatus, circuit data for a circuit diagram created through circuit design processing is stored in a circuit database. Based on the circuit data stored in the circuit database, the respective logic types of components are discriminated and set for the component in the circuit data. Moreover, by adding logically transparent nets to the circuit data stored in the circuit database, DRC data dedicated to a DRC is created and stored in a DRC database. A DRC execution unit performs the DRC, by utilizing the DRC data stored in the DRC database.
Public/Granted literature
- US20080005708A1 Verification apparatus, design verification method, and computer aided design apparatus Public/Granted day:2008-01-03
Information query