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US07657850B2 Chip level scan chain planning for hierarchical design flows 有权
芯片级扫描链规划用于分层设计流程

Chip level scan chain planning for hierarchical design flows
Abstract:
A scan chain planning method uses physical data with a hierarchical design to optimize chip level scan chains. Specifically, location data of physical blocks is used to determine optimal partitioning of the hierarchical design to balance chip level scan chains and reduce the number block scan ports by determining optimal locations for the block scan ports. Actual layout of the scan chains is based on the locations of the block scan ports and the number of scan elements determined by the method for each block scan chain.
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