Invention Grant
- Patent Title: Chip level scan chain planning for hierarchical design flows
- Patent Title (中): 芯片级扫描链规划用于分层设计流程
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Application No.: US11638292Application Date: 2006-12-12
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Publication No.: US07657850B2Publication Date: 2010-02-02
- Inventor: Lin Huang , Huaming Hu
- Applicant: Lin Huang , Huaming Hu
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Silicon Valley Patent Group, LLP
- Agent Edward S. Mao
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A scan chain planning method uses physical data with a hierarchical design to optimize chip level scan chains. Specifically, location data of physical blocks is used to determine optimal partitioning of the hierarchical design to balance chip level scan chains and reduce the number block scan ports by determining optimal locations for the block scan ports. Actual layout of the scan chains is based on the locations of the block scan ports and the number of scan elements determined by the method for each block scan chain.
Public/Granted literature
- US20080141086A1 Chip level scan chain planning for hierarchical design flows Public/Granted day:2008-06-12
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