Invention Grant
- Patent Title: Low power testing of very large circuits
- Patent Title (中): 低功耗测试非常大的电路
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Application No.: US12351528Application Date: 2009-01-09
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Publication No.: US07657811B2Publication Date: 2010-02-02
- Inventor: Lee D. Whetsel
- Applicant: Lee D. Whetsel
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.
Public/Granted literature
- US20090119560A1 LOW POWER TESTING OF VERY LARGE CIRCUITS Public/Granted day:2009-05-07
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