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US07657811B2 Low power testing of very large circuits 有权
低功耗测试非常大的电路

Low power testing of very large circuits
Abstract:
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.
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