Invention Grant
US07657773B1 Clock distribution chip for generating both zero-delay and non-zero-delay clock signals
有权
用于产生零延迟和非零延迟时钟信号的时钟分配芯片
- Patent Title: Clock distribution chip for generating both zero-delay and non-zero-delay clock signals
- Patent Title (中): 用于产生零延迟和非零延迟时钟信号的时钟分配芯片
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Application No.: US11425881Application Date: 2006-06-22
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Publication No.: US07657773B1Publication Date: 2010-02-02
- Inventor: Shyam Chandra , Om Agrawal , Ludmil Nikolov , Harald Weller , Douglas Morse
- Applicant: Shyam Chandra , Om Agrawal , Ludmil Nikolov , Harald Weller , Douglas Morse
- Applicant Address: US OR Hillsboro
- Assignee: Lattice Semiconductor Corporation
- Current Assignee: Lattice Semiconductor Corporation
- Current Assignee Address: US OR Hillsboro
- Agency: Mendelsohn, Drucker & Associates, P.C.
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F1/04
Abstract:
In one embodiment of the invention, a clock distribution (CD) chip has one or more input pins, input buffer circuitry, clock generation and distribution circuitry, fanout circuitry, one or more output pins, a feedback pin, and feedback buffer circuitry. Based on single-ended or differential input clock signals applied to the input pins, the CD chip can be programmably configured to generate zero, one, or more zero-delay (ZD) output clock signals and zero, one, or more non-zero-delay (NZD) output clock signals for simultaneous presentation at the output pins.
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