Invention Grant
US07656729B2 Circuit and method for decoding column addresses in semiconductor memory apparatus
失效
用于解码半导体存储装置中的列地址的电路和方法
- Patent Title: Circuit and method for decoding column addresses in semiconductor memory apparatus
- Patent Title (中): 用于解码半导体存储装置中的列地址的电路和方法
-
Application No.: US11961998Application Date: 2007-12-20
-
Publication No.: US07656729B2Publication Date: 2010-02-02
- Inventor: Hong-Sok Choi
- Applicant: Hong-Sok Choi
- Applicant Address: KR
- Assignee: Hynix Semiconductor, Inc.
- Current Assignee: Hynix Semiconductor, Inc.
- Current Assignee Address: KR
- Agency: Baker & McKenzie LLP
- Priority: KR10-2007-0014572 20070212
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C8/00
Abstract:
A column address decoding circuit of a semiconductor memory apparatus includes a predecoder configured to combine a column address and a decoding test signal, thereby outputting a decoding address. A main decoder receives the decoding address, thereby outputting a plurality of column select signals.
Public/Granted literature
- US20080192562A1 CIRCUIT AND METHOD FOR DECODING COLUMN ADDRESSES IN SEMICONDUCTOR MEMORY APPARATUS Public/Granted day:2008-08-14
Information query
