Invention Grant
- Patent Title: Semiconductor memory system including a plurality of semiconductor memory devices
- Patent Title (中): 半导体存储器系统包括多个半导体存储器件
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Application No.: US12027546Application Date: 2008-02-07
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Publication No.: US07656711B2Publication Date: 2010-02-02
- Inventor: Noboru Shibata , Hiroshi Sukegawa
- Applicant: Noboru Shibata , Hiroshi Sukegawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-030789 20070209
- Main IPC: G11C16/04
- IPC: G11C16/04
Abstract:
A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
Public/Granted literature
- US20080192548A1 SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES Public/Granted day:2008-08-14
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