Invention Grant
- Patent Title: Stratified underfill in an IC package
- Patent Title (中): IC封装中分层的底部填充物
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Application No.: US11393050Application Date: 2006-03-29
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Publication No.: US07656042B2Publication Date: 2010-02-02
- Inventor: Mirng-Ji Lii , Szu Wei Lu , Tjandra Winata Karta , Chien-Hsiun Lee
- Applicant: Mirng-Ji Lii , Szu Wei Lu , Tjandra Winata Karta , Chien-Hsiun Lee
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Agent Steve E. Koffs
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.
Public/Granted literature
- US20070238220A1 Stratified underfill in an IC package Public/Granted day:2007-10-11
Information query
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