A package substrate (16) for electrically connecting an integrated circuit (12) to a printed circuit board (14) includes a core (222c), a patterned conductive layer (220c), a plurality of spaced apart, discrete capacitors (230), and an insulating layer (222b). The patterned conductive layer (220c) is positioned on the core (222c). The discrete capacitors (230) are electrically connected to the patterned conductive layer (220c). The insulating layer (222b) covers the patterned conductive layer (220c) and separates the capacitors (230). The capacitors (230) are positioned to provide a relatively low impedance path for quick access to power to stabilize the voltage delivered to the integrated circuit (12), and the capacitors (230) do not occupy valuable space on the integrated circuit (12), and the printed circuit board (14). Further, this placement of the capacitor assembly (18) allows for use of a relatively large number of discrete capacitors (230) without taking up valuable space from the surface of the package substrate (16).