Invention Grant
- Patent Title: Low threshold voltage semiconductor device with dual threshold voltage control means
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Application No.: US11259644Application Date: 2005-10-26
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Publication No.: US07655994B2Publication Date: 2010-02-02
- Inventor: Eduard A. Cartier , Mathew W. Copel , Martin M. Frank , Evgeni P. Gousev , Paul C. Jamison , Rajarao Jammy , Barry P. Linder , Vijay Narayanan
- Applicant: Eduard A. Cartier , Mathew W. Copel , Martin M. Frank , Evgeni P. Gousev , Paul C. Jamison , Rajarao Jammy , Barry P. Linder , Vijay Narayanan
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Louis J. Percello, Esq.
- Main IPC: H01L29/94
- IPC: H01L29/94 ; H01L21/326
Abstract:
A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.
Public/Granted literature
- US20070090471A1 Low threshold voltage semiconductor device with dual threshold voltage control means Public/Granted day:2007-04-26
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