Invention Grant
- Patent Title: Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same
- Patent Title (中): 单片集成增强模式和耗尽型场效应晶体管及其制作方法
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Application No.: US11248935Application Date: 2005-10-11
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Publication No.: US07655546B2Publication Date: 2010-02-02
- Inventor: Walter Anthony Wohlmuth
- Applicant: Walter Anthony Wohlmuth
- Applicant Address: US OR Hillsboro
- Assignee: TriQuint Semiconductor, Inc.
- Current Assignee: TriQuint Semiconductor, Inc.
- Current Assignee Address: US OR Hillsboro
- Agency: Bever, Hoffman & Harms, LLP
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L31/072
Abstract:
A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.
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