Invention Grant
US07655515B2 Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide
失效
具有横向延伸结构的横向DMOS结构,用于减少栅极氧化物中的电荷捕获
- Patent Title: Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide
- Patent Title (中): 具有横向延伸结构的横向DMOS结构,用于减少栅极氧化物中的电荷捕获
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Application No.: US11080146Application Date: 2005-03-15
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Publication No.: US07655515B2Publication Date: 2010-02-02
- Inventor: James D. Beasom
- Applicant: James D. Beasom
- Applicant Address: US CA Irvine
- Assignee: Intersil Americas Inc.
- Current Assignee: Intersil Americas Inc.
- Current Assignee Address: US CA Irvine
- Agency: Fogg & Powers LLC
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.
Public/Granted literature
- US20050214995A1 Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide Public/Granted day:2005-09-29
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