Invention Grant
US07652513B2 Slave latch controlled retention flop with lower leakage and higher performance
有权
从锁存控制保持触发器具有较低的泄漏和更高的性能
- Patent Title: Slave latch controlled retention flop with lower leakage and higher performance
- Patent Title (中): 从锁存控制保持触发器具有较低的泄漏和更高的性能
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Application No.: US11895853Application Date: 2007-08-27
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Publication No.: US07652513B2Publication Date: 2010-01-26
- Inventor: Bindu Prabhakar Rao , Sumanth Katte Gururajarao , Dharin N. Shah
- Applicant: Bindu Prabhakar Rao , Sumanth Katte Gururajarao , Dharin N. Shah
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Dawn V. Stephens; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03K3/356
- IPC: H03K3/356

Abstract:
In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.
Public/Granted literature
- US20090058484A1 Slave latch controlled retention flop with lower leakage and higher performance Public/Granted day:2009-03-05
Information query
IPC分类: