Invention Grant
US07647543B2 Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets
有权
可重复编程的现场可编程门阵列，具有集成系统，可减轻单个事件扰乱的影响
- Patent Title: Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets
- Patent Title (中): 可重复编程的现场可编程门阵列，具有集成系统，可减轻单个事件扰乱的影响
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Application No.: US11535574Application Date: 2006-09-27
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Publication No.: US07647543B2Publication Date: 2010-01-12
- Inventor: Tak-kwong Ng , Jeffrey A. Herath
- Applicant: Tak-kwong Ng , Jeffrey A. Herath
- Applicant Address: US DC Washington
- Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
- Current Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
- Current Assignee Address: US DC Washington
- Agent Helen M. Galus
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G08C25/02 ; G11C29/00
Abstract:
An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.
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