Invention Grant
- Patent Title: Adaptive bandwidth phase locked loops with current boosting circuits
- Patent Title (中): 带电流升压电路的自适应带宽锁相环
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Application No.: US11826901Application Date: 2007-07-19
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Publication No.: US07646226B2Publication Date: 2010-01-12
- Inventor: Byung-chul Kim
- Applicant: Byung-chul Kim
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2006-0079466 20060822
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
An adaptive bandwidth phase locked loop (PLL) includes a phase frequency detector configured to generate a comparison pulse having a pulse-width and sign corresponding to a difference between a reference frequency and a first frequency. A pulse-voltage converter is configured to generate a control voltage corresponding to the comparison pulse. An oscillator is configured to generate the output frequency corresponding to the control voltage.
Public/Granted literature
- US20080048741A1 Adaptive bandwidth phase locked loops with current boosting circuits Public/Granted day:2008-02-28
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