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US07646226B2 Adaptive bandwidth phase locked loops with current boosting circuits 失效
带电流升压电路的自适应带宽锁相环

Adaptive bandwidth phase locked loops with current boosting circuits
Abstract:
An adaptive bandwidth phase locked loop (PLL) includes a phase frequency detector configured to generate a comparison pulse having a pulse-width and sign corresponding to a difference between a reference frequency and a first frequency. A pulse-voltage converter is configured to generate a control voltage corresponding to the comparison pulse. An oscillator is configured to generate the output frequency corresponding to the control voltage.
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