Invention Grant
- Patent Title: Wafer level pre-packaged flip chip systems
- Patent Title (中): 晶圆级预封装倒装芯片系统
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Application No.: US11460435Application Date: 2006-07-27
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Publication No.: US07646102B2Publication Date: 2010-01-12
- Inventor: Suan Jeung Boon
- Applicant: Suan Jeung Boon
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lunberg & Woessner, P.A.
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L21/469

Abstract:
Flip chip packages formed at a wafer level on semiconductor wafers for electronic systems provide convenient prepackaging. The package, in one embodiment, includes an adhesive layer applied to an active side of the wafer. The adhesive layer has openings to permit access to the conductive pads on each die. A conductive material substantially fills the openings. A pre-packaged die diced from the semiconductor wafer is mounted to a support wherein the conductive material effects electrical interconnection between the conductive pads on the die and receiving conductors on the support. The pre-packaged die can be coupled to a processor for an electronic system. To provide greater mounting densities, two or more dice may be coupled with the adhesive layer providing a covering for the two or more dice. The prepackaged chip with two or more dice may be coupled to a processor reducing the volume needed in an electronic system.
Public/Granted literature
- US20060261493A1 Wafer level pre-packaged flip chip systems Public/Granted day:2006-11-23
Information query
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