Invention Grant
- Patent Title: Semiconductor device and manufacturing method thereof
- Patent Title (中): 半导体装置及其制造方法
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Application No.: US11729765Application Date: 2007-03-28
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Publication No.: US07646101B2Publication Date: 2010-01-12
- Inventor: Ryotaro Yagi , Shinichi Chikaki , Yoshinori Shishida
- Applicant: Ryotaro Yagi , Shinichi Chikaki , Yoshinori Shishida
- Applicant Address: JP Kyoto JP Tokyo JP Osaka
- Assignee: Rohm Co., Ltd.,NEC Corporation,Sanyo Electric Co., Ltd.
- Current Assignee: Rohm Co., Ltd.,NEC Corporation,Sanyo Electric Co., Ltd.
- Current Assignee Address: JP Kyoto JP Tokyo JP Osaka
- Agency: Fish & Richardson P.C.
- Priority: JP2006-091666 20060329
- Main IPC: H01L29/40
- IPC: H01L29/40

Abstract:
An insulating layer is formed on a semiconductor substrate, and has a through hole for via. A porous silica layer has a trench for interconnection communicating to the through hole for via, and is formed on the insulating layer in contact therewith. A conductive layer is formed in the through hole for via and in the trench for interconnection. The insulating layer is formed from a material containing carbon, hydrogen, oxygen, and silicon, and having absorption peak attributed to Si—CH3 bond in a range from at least 1260 cm−1 to at most 1280 cm−1 (around 1274 cm−1) when measured with FT-IR. Thus, a semiconductor device having a porous insulating layer in which depth of the trench for interconnection is readily controlled, a dielectric constant is low, and increase in leakage current is less likely, as well as a manufacturing method thereof can be obtained.
Public/Granted literature
- US20070228528A1 Semiconductor device and manufacturing method thereof Public/Granted day:2007-10-04
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