Invention Grant
US07646091B2 Semiconductor package and method using isolated Vss plane to accommodate high speed circuitry ground isolation
有权
采用隔离Vss平面的半导体封装和方法，适应高速电路接地隔离
- Patent Title: Semiconductor package and method using isolated Vss plane to accommodate high speed circuitry ground isolation
- Patent Title (中): 采用隔离Vss平面的半导体封装和方法，适应高速电路接地隔离
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Application No.: US11399723Application Date: 2006-04-06
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Publication No.: US07646091B2Publication Date: 2010-01-12
- Inventor: Maurice O. Othieno , Chok J. Chia , Amar J. Amin
- Applicant: Maurice O. Othieno , Chok J. Chia , Amar J. Amin
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Beyer Law Group LLP
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
Public/Granted literature
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