Invention Grant
- Patent Title: Programmable logic device with performance variation compensation
- Patent Title (中): 具有性能变化补偿的可编程逻辑器件
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Application No.: US11269019Application Date: 2005-11-07
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Publication No.: US07644385B1Publication Date: 2010-01-05
- Inventor: Peter Boyle , Iliya Zamek
- Applicant: Peter Boyle , Iliya Zamek
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Treyz Law Group
- Agent G. Victor Treyz
- Main IPC: H03K17/693
- IPC: H03K17/693

Abstract:
Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to produce configuration data containing alternative configuration memory settings each of which is optimized for programmable logic devices with different performance characteristics. During manufacturing, programmable logic devices are tested to identify their performance characteristics. A bin code is stored in non-volatile memory in each device to specify which performance characteristics are associated with that device. During programming, the bin code of a given device is used to decide which of the alternative configuration memory settings are to be discarded. The retained subset of the configuration data is loaded into configuration memory in the given device.
Information query
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