Invention Grant
US07644336B2 Techniques for providing greater error protection to error-prone bits in codewords generated from irregular codes
有权
为从不正规代码产生的码字中的错误位提供更大的错误保护的技术
- Patent Title: Techniques for providing greater error protection to error-prone bits in codewords generated from irregular codes
- Patent Title (中): 为从不正规代码产生的码字中的错误位提供更大的错误保护的技术
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Application No.: US11346836Application Date: 2006-02-04
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Publication No.: US07644336B2Publication Date: 2010-01-05
- Inventor: Sizhen Yang , Yuan Xing Lee , Shaohua Yang
- Applicant: Sizhen Yang , Yuan Xing Lee , Shaohua Yang
- Applicant Address: NL Amsterdam
- Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
- Current Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
- Current Assignee Address: NL Amsterdam
- Agent Steven J. Cahill
- Main IPC: H03M13/00
- IPC: H03M13/00
Abstract:
Greater error protection is provided to error-prone bits that are generated from irregular soft-decoded error correction codes. Error protection is increased to error-prone bits that of interest in a particular system (e.g., parity check bits). One or more extra bits are added to each codeword in the encoding process. The one or more extra bits correspond to lower weights. The one or more extra bits are discarded after each codeword is decoded.
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