Invention Grant
- Patent Title: Integrated circuit testing method and related circuit thereof
- Patent Title (中): 集成电路测试方法及其相关电路
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Application No.: US11853023Application Date: 2007-09-11
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Publication No.: US07644329B2Publication Date: 2010-01-05
- Inventor: Chung-Hsin Chiang
- Applicant: Chung-Hsin Chiang
- Applicant Address: TW Taipei
- Assignee: ALI Corporation
- Current Assignee: ALI Corporation
- Current Assignee Address: TW Taipei
- Agent Winston Hsu
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A chip with an integrated circuit testing function includes a selecting unit positioned before a flip-flop of a scan chain, where the scan chain connects a scan-in pad, a scan-out pad and the flip-flop. When the chip is packaged and the scan-in pad does not connect to a pin of a package, the selecting unit selects a scan-in signal from another scan chain and transmits the scan-in signal from the another scan chain to the flip-flop; and when the chip is packaged and the scan-in pad connects to a pin of the package, the selecting unit selects a scan-in signal from the scan-in pad and transmits the scan-in signal from the scan-in pad to the flip-flop.
Public/Granted literature
- US20090070645A1 INTEGRATED CIRCUIT TESTING METHOD AND RELATED CIRCUIT THEREOF Public/Granted day:2009-03-12
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