A controller includes a volatile random access memory and translation hardware. The volatile random access memory includes a table having at least one entry. The at least one entry includes a portion of a physical address of a memory location at a NAND flash non-volatile solid-state memory. The volatile random access memory is accessible to the translation hardware. The translation hardware is configured to sum binary data bits of a portion of a logical address and a pointer value to determine a random access memory address of the at least one entry and is configured to determine the portion of the physical address of the memory location at the NAND flash non-volatile solid-state memory based at least in part on the random access memory address of the at least one entry.