Invention Grant
US07644237B1 Method and apparatus for global ordering to insure latency independent coherence
有权
用于全局排序以确保延迟独立相干性的方法和装置
- Patent Title: Method and apparatus for global ordering to insure latency independent coherence
- Patent Title (中): 用于全局排序以确保延迟独立相干性的方法和装置
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Application No.: US10783960Application Date: 2004-02-20
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Publication No.: US07644237B1Publication Date: 2010-01-05
- Inventor: Thomas A. Petersen , Sanjay Vishin
- Applicant: Thomas A. Petersen , Sanjay Vishin
- Applicant Address: US CA Mountain View
- Assignee: MIPS Technologies, Inc.
- Current Assignee: MIPS Technologies, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to apply global ordering to the requests. A bus interface having request, snoop, and response logic is provided for each agent. A bus interface having request, snoop and response logic is provided for the global arbiter, and a bus interface is provided to couple the global arbiter to each type of fabric it is responsible for. Global ordering and arbitration logic tags incoming requests from the multiple agents and insures that snoops are responded to according to the global order, without regard to latency differences in the fabrics.
Information query