Invention Grant
US07644233B2 Apparatus and method for supporting simultaneous storage of trace and standard cache lines
有权
用于支持跟踪标准缓存行的同时存储的装置和方法
- Patent Title: Apparatus and method for supporting simultaneous storage of trace and standard cache lines
- Patent Title (中): 用于支持跟踪标准缓存行的同时存储的装置和方法
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Application No.: US11538445Application Date: 2006-10-04
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Publication No.: US07644233B2Publication Date: 2010-01-05
- Inventor: Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
- Applicant: Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Joscelyn G. Cockburn; Mark E. McBurney; Daniel E. McConnel
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
Public/Granted literature
- US20080086596A1 Apparatus and Method for Supporting Simultaneous Storage of Trace and Standard Cache Lines Public/Granted day:2008-04-10
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