A processor including an integrated system interface unit configured to manage multiple I/O interfaces and multiple protocols. A processor includes a plurality of processing cores, a cache comprising a plurality of banks, and a system interface unit coupled to the processing cores and the cache. The system interface unit includes an inbound unit configured to receive inbound transactions from a first I/O unit and a second I/O unit, and an outbound unit configured to convey outbound transactions to either the first I/O unit or the second I/O unit. Each of the first and second I/O units is configured to support different protocols. Prior to conveying transaction data to the system interface, the first I/O unit and second I/O units reformat transaction data to conform to a common format. The system interface receives and stores transaction data in either queues dedicated for cacheable transactions or queues dedicated for non-cacheable transactions. In addition, each of the I/O units may also indicate in the common format whether a given transaction is to be ordered with respect to other transactions. The system interface may separately store ordered transactions from those which are non-ordered.